Should non-functional Pads become Removed or Kept in Vias of

2019-11-29 14:06Writer: qyadminReading:

non functional pads pcb problem

      Non-functional pads are an issue in the PCB design industry. that still lacks consensus. Debates about reliability and effects on signal integrity abound. While most designers and engineers agree that the debate on signal integrity settled. the reliability debate still rages on behind the scenes. Since no general rules about non functional pads exist. designers will need to determine. if they should ditch non-functional pads in their specific applications.
      The presence of non-functional pads on plated. through hole vias can lead to a condition known as “telegraphing”. When there is so much copper at the vias, the material between pads becomes resin starved. As a result, an image of the copper stack appears as peaks and valleys in the surface layers of the dielectric. In other words, the image of the copper stack is "telegraphed" to the board surface.
       When the copper is thicker than the dielectric layer between pads. the condition exacerbated and reliability reduced. The high spots create regions where epoxy can squeezed out. leaving voids between neighboring pads. Voids usually form at the right angle formed by the pad and via barrel, leading to thermal failure at the joint. The effective cross-sectional area of the joint shrinks over time. resulting in increased current density.
      Void formation at via joints results in adhesion issues. and allows electrochemical migration paths. This can cause growth of dendritic or fibrous structures. between pads due to the slight voltage difference between them. Growth of these structures accumulates over time. leading to PCB failure that is difficult to diagnose.
      If dendritic structures can bridge the gap between adjacent conductors. a sudden drop in resistance occurs. as these structures grow in parallel with the via. If the cross-sectional area of the dendrite is small. the current density will be high and the structure may burn out. eliminating the fault. This leads to an intermittent failure behavior that is difficult to diagnose.
      In many situations, non-functional pads are harmless. Fabricators generally prefer that non-functional pads e removed because it makes drilling easier. There are debates over reliability that relate to the via aspect ratio. Whether you should remove non-functional pads depends on the application and operating conditions. Strain buildup in the copper plating along the via barrel. during thermal cycling can lead to cracking, depending on the via aspect ratio.
      In low aspect ratio vias, the interior copper. plating is more uniform, and nonfunctional pads. can increase the lifetime of the via. The combination of anchoring provided. by the pad and the more uniform in the via barre.l causes the via to be less prone to cracking. In high aspect ratio vias. the via barrel is more prone to cracking at the center. due to the thinner copper coating in the center of the via barrel. regardless of the presence of non-functional pads.
      Non-functional pads take up valuable real estate. on the inner layers in thinner multilayer HDI boards. As long as you can be sure the board will remain stable under thermal cycling. it may be desirable to remove non-functional pads. to improve trace routing on inner layers.
      Removing non-functional pads is a great way to gain some extra space on the inner layers of any PCB. But, caution should used when designing flex and rigid-flex PCBs. Copper in a plated through-hole via does not bond to a flexible substrate as well as it bonds to a rigid substrate. Since copper bonding is a real issue in flexible substrates. non functional pads now become useful.
      Bonding is especially important in controlled impedance flex. and rigid-flex boards, where thicker dielectric layers used to build the material stack-up. All pads, both functional and non-functional. function as anchor points that dispersed along the via barrel. This increases the strength of the via in a flexible board.
      Some manufacturers recommend leaving. at least some non functional pads on flex and rigid-flex boards. If all non-functional pads along a via removed. the gap between functional pads becomes very large. and the plating may start to separate from the hole wall. If possible, these pads should be  dispersed along the via barrel to distribute strain . This will keep the plating from cracking or separating from the substrate.

         High-speed indicators is a hot subject that can't prevented by communication industries. With the boost amount of transmitted info and transmission speed price. high-speed signals have become significant. High-velocity PCB is usually a loading table of high-speed indicators. and its materials selection, production technology. and routing style all impact quality of high-speed signals. nonfunctional Pad. aka NFP, is definitely a technological solution to manufacture high-rate. PCB while insertion reduction. is one of the most crucial parameters indicating transmission quality. To remove or even to keep NFP offers been an inevitable conversation topic. between engineers and producers. This article analyzes impact of NFP on insertion lack of high-speed indicators. from the perspective of production procedure within an experimental technique. and manuals you to the solution of whether to drop or even to keep unused pads.

Should we keep nn.functional.pad


       Introduction of NFP

        nonfunctional pads are pads upon external or internal layers that aren't. connected to any energetic conductive patterns upon the layer. NFP does not have any influence on any electric signal transmission nonetheless. it is with the capacity of strengthening copper adhesion on hole wall structure.
        Adding NFP means offering metal attachment points before PTH (Plated Through Hole) copper. so plenty of manufacturers have a tendency to add NFP to be able to ensure better aftereffect of PTH copper. along the way of multi-layer PCB production .

        Experiment Design

        In this experiment, the same CCL (Copper Clad Laminate) materials chosen. All PCBs contain 20 layers among which routing applied on the 3rd and eighteenth coating. Insertion loss could be in comparison between adding NFP (Scheme 1). and eliminating NFP (Scheme 2) to be able to make sure whether NFP has impact on transmission quality. Because many uncertain components do exist along the way of PCB production. the key parameters need to inspected aside from insertion loss to guarantee . no more influence elements combined into manufacturing.

       Influencing Elements Inspection

       • Impedance consistency inspection
        In the signal loss test, signal reflection generated. because of inconsistent impedance, that may finally influence test consequence of insertion loss. So, correctness of insertion reduction test depends upon the standard of impedance consistency.
        Test Scheme Test Coating Characteristic Impedance (Ohm)
         Scheme1 3rd layer 113.03
         Scheme2 3rd layer 112.71
         Scheme1 18th layer 111.93
         Scheme2 18th layer 114.07
         Predicated on above table, it could noticed. that impedance difference falls inside 5% between two schemes with a summary. that influence of feature impedance upon loss test could neglected.

         • Elements influencing insertion reduction inspection

         Insertion loss made up by dielectric reduction and conductor loss. As the same materials and light painting images. used in two schemes inspected in this experiment. dielectric reduction and conductor loss result from PCB production. Next, both items will end up analyzed to be able to ensure noninfluence on PCB manufacturing.
         a. Dielectric loss inspection
         Software of adhesive bonding sheet in multi-layer stacking. will produce some resin economic downturn and various amount of resin economic downturn. leads to variations. between dielectric reduction. In conditions of uncertainty of resin economic downturn on adhesive bonding sheet. x-section analysis needs to applied after stacking up to be able to eliminate impact. owing to difference in conditions of resin recession amount.
        Through the analysis, it could summarized. that core thickness of upper layer and lower layer of both schemes is 139.8μm and 135.2μm. After stacking up, thickness of adhesive bonding sheet is 257.4μm and 251.9μm. The utmost thickness difference falls within 6μm, providing to manufacturing tolerance necessity. and insertion loss will not influenced because of the dielectric loss.
          b. Conductor loss inspection
Conductor reduction, then. related to length of lines, surface area roughness and lateral erosion. during PCB production process in check circuit. In both schemes of the experiment, circuit design may be the same with the impact of line size eliminated. Brown effect, focus of etching answer. and drinking water pressure all have impact to surface roughness. to avoid these complicated components. circuit consistency is straight judged from the ultimate result.
Through the experiment, transmission line width measured to be 168μm and 166μm with the use of Scheme 1. and Scheme 2 and transmission line height 18.3μm and 18.9μm. Surface area roughness both stay at 2.5μm. All the data say that conductor reduction is similar. when it comes to transmission line manufacturing to. ensure that impact of conductor reduction on insertion loss could eliminated.

         NFP Influence Analysis

         Starting from generation way to get dielectric reduction. and conductor loss, in conjunction with generation theory of insertion reduction. many inspections applied with regards to PCB manufacturing consistency to be able. to ensure only 1 variable, which is usually NFP, occurs in both schemes。
          Due to the only variable, NFP. influence of NFP on transmission insertion loss could be approximately judged. Scheme 1 eliminates NFP while Scheme 2 maintains NFP. It could noticed from the determine. above that either level 03 or layer 18, insertion loss test lead to Scheme 1 is definitely. all smaller sized than that of Scheme 2. which shows that adding NFP will improve signal insertion loss.
          Hardly any insertion loss difference occurs between almost all ranks of components. If the insertion reduction inspected. in this experiment falls within the group of threshold. material quality will reduced by NFP. that will influence the complete production line from materials manufacturer to end.

Other PCB part

A PCB like a layer cake or lasagna- there are alternating layers of different materials. which  laminated together with heat and adhesive such that the result is a single object.


      The base material, or substrate, is usually fiberglass.  the most common designator for this fiberglass is "FR4". This solid core gives the PCB its rigidity and thickness. There are also flexible PCBs built . on flexible high-temperature plastic (Kapton or the equivalent).

Perf board

     Cheaper PCBs and perf boards (shown above). will  made with other materials such as epoxies or phenolics. which lack the durability of FR4 but are much less expensive. You will know you are working with this type of PCB when you solder to it - they have a very distictive bad smell. These types of substrates are also found in low-end consumer electronics. Phenolics have a low thermal decomposition temperature which causes them to delaminate. smoke and char when the soldering iron held too long on the board.


     The next layer is a thin copper foil, which laminated to the board with heat and adhesive. On common, double sided PCBs, copper applied to both sides of the substrate. In lower cost electronic gadgets the PCB may have copper on only one side. When we refer to a double sided or 2-layer board we are referring to the number of copper layers (2) in our lasagna. This can be as few as 1 layer or as many as 16 layers or more.

Exposed Copper on PCB

       PCB with copper exposed, no solder mask or silkscreen.
The copper thickness can vary and specified by weight, in ounces per square foot. The vast majority of PCBs have 1 ounce of copper per square foot but some PCBs. that handle very high power may use 2 or 3 ounce copper. Each ounce per square translates to about 35 micrometers or 1.4 thousandths of. an inch of thickness of copper.


    The layer on top of the copper foil called the soldermask layer. This layer gives the PCB its green (or, at SparkFun, red) color. It is overlaid onto the copper layer to. insulate the copper traces from accidental contact with other metal, solder. or conductive bits. This layer helps the user to solder to the correct places and prevent solder jumpers.
     In the example below, the green solder mask applied to the majority of the PCB. covering up the small traces but leaving the silver rings and SMD pads exposed so they can soldered to.

Green Solder Mask

      Soldermask is most green in color but any color is possible. We use red for almost all the SparkFun boards, white for the IOIO board, and purple for the LilyPad boards.


    The white silkscreen layer applied on top of the soldermask layer. The silkscreen adds letters, numbers, and symbols to the PCB. that allow for easier assembly. and indicators for humans to better understand the board. We often use silkscreen labels to state what the function of each pin or LED.

PCB with silkscreen

    Silkscreen is most white but any ink color can used. Black, gray, red, and even yellow silkscreen colors are available. it is, but, uncommon to see more than one color on a single board.


          When involves high-speed PCBs, multi-layer PCBs are inevitable the advancement pattern. and through via production is the 1st problem. NFP features great improvement to PTH copper along the way of production PCB. via wall structure and plays a effective part in stopping via copper from dropping. and coping with quality complications such as via wall structure crack. Eliminating various other influencing elements. the adjustable of NFP known as in this post and impact of NFP on insertion reduction analyzed to ensure. that it is with the capacity of providing some mention of material manufacturer. PCB producer and terminal manufacturer in conditions of high-speed PCB design. 
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