How to design High-Speed PCB
2018-12-06 11:47Writer: qyadminReading:
High-Speed PCB Design
• Stackup and layout
Stackup design is the most important problem that needs to be considered and affordable stackup design can inhibit EMI (Elcetromagnetic Interference) rays, making transient voltage on power plane or floor layer be no more than possible and shielding the electromagnetic field of transmission and power. Generally, multi-layer table and multiple capabilities are applied in high-speed digital circuit design. PCB stacking design is applied based on extensive elements including circuit clock frequency, PCB fabrication cost, pin density, production period and reliability. Furthermore, layers of multi-layer panel should be managed symmetrical and the amount of planks should be a straight quantity since asymmetrical stacking design may cause warpage of planks. The password cards designed in this specific article is linked with Personal computer through PCIE slot machine and the scale and form of the circuit table is set with the elevation around 67mm and size around 174mm, configuring PCIE By4 user interface pin in the bottom. Due to the high element density and solid routing, the amount of PCB layers is found as 6 layers with distribution of transmission layer, power coating, signal level, power layer, surface layer, signal coating. This design that contains 3 transmission layers, 1 floor level and 2 power layers, providing the surroundings required by transmission integrity.
Following the dedication of PCB stacking, element groups and design should be applied. First, position of components needs to be programmed relative to the dimension and design of PCB, taking line-connection, practical partitioning and cut and beauty between components under consideration. Then, components need to be fairly distributed in accordance to different marks of element voltage to make voltage cables as short as you possibly can, which is with the capacity of reducing the interference of power sound and increasing balance of power. Chip positioning should focus on the partnership between its auxiliary circuit and its own chip and also to keeping crystal oscillator behind clock pins. High-noise components should be avoided being positioned around crystal oscillator and really should be near its traveling components. Furthermore, the keeping each chip power and transmission pins needs to be considered using their positions and path adjusted predicated on the linked lines. As the ratio of length of password cards is more than 2:1 with the positions of PCIE slot machine, loading openings and indicating LED set, element layout for set components needs to be considered first in element layout. Furthermore, consequently of the large numbers of linking lines between element and FPGA, the element design should be applied with FPGA as a middle prior to positions of other components so the top and bottom level room of PCB can be effectively found in order to leave enough room between components and components and placement holes.
• Power design
In high-speed circuit plank design, design of power system is straight related to the success of the complete system. Noise produced by power and surface should be reduced to the minimal in order to guarantee the reliability of products. The use of power distribution plan in the technique of layers identifies the actual fact that power is distributed through the metallic overall layer, reducing power impedance and sound and increasing reliability. Because multiple capabilities are worried by PCB, multi-power coating design should be employed, capable of removing general public impedance coupling interference as a sound loop. The use of decoupling capacitance is with the capacity of solving the issue of power integrity since capacitor can be only positioned on underneath level or top coating of PCB, predicated on which cables hooking up decoupling capacitors should be brief and wide. In accordance to chip materials, the current moving through power lines can be calculated and width of leads can be decided. The wider leads are, the greater current they can bring. The experimental method is illustrated as: W(collection width: mm) ≥ L(mm/A) x I(current: A)
Multiple capabilities on PCB obtain a couple of types of power from power table using back panel and the energy is then changed into other power required by components. The transformation of power is split into two architectures: centralized power structures and distributed power structures. The former identifies power comes by an unbiased power and then changed into all types of required powers as the latter identifies multi-grade power transformation. Because centralized power structures features drawbacks of high cost and large PCB area, distributed power structures is applied in this design. Cryptographical credit card concerns 6 forces, including 12V, 3.3V, 5V, 2.5V, 1.2V and 1.8V. This design begins with the involvement of 3.3V and 12V power in PCIE slot machine and then 3.3V power is with the capacity of producing 5V power and 1.8V power through voltage transformation chip, providing power for plug-in and chip 3. Next, 12V power is changed into 2.5V capacity to supply power for FPGA and chip 4. Finally, 2.5V power is changed into 1.2V capacity to supply power for FPGA and chip 2. The distributed power structures of cryptographical credit card is shown in Determine 2 below.
• Through-hole design
Along the way of design for multi-layer PCBs with high density, through openings should be employed, transmitting signal in one layer to some other level to provide electric communication between layers. Position design of through openings needs to be applied with much treatment. Through openings mustn't be positioned on pad and one imprinted line can be employed for connection, or else resulting in problems such as tombstone and inadequate solder. Soldermask needs to be covered on through opening pad with distance arranged to be 4 mil and through openings mustn't be positioned at the guts of pad for chip components on soldering part. The positioning of thru-holes is illustrated in Physique 3 below.
Furthermore, thru-hole position mustn't be too close to goldfinger whose plug-in aspect should contain chamfer. To make circuit boards connected in PCIE slot machine, chamfer of (1~1.5)x45° can be designed on two side edges of plug-in plank.
• High-speed transmission routing
Along the way of routing, distribution needs to be modified fairly to make linking lines the minimal so that crosstalk can be reduced. Along the way of high-speed digital transmission routing, signal coating near multi-power level routing should be a long way away from power reference surface to avoid the era of returning route by transmission current.
Since high-speed circuit clock transmission frequency is relatively high, the jitter, drifting and deformation greatly impact the machine so that high-speed PCB design requires small transmission influx interference. Therefore, the issue of clock distribution and routing should be first of all considered. Routing needs to be applied on high-speed clock indicators and the routing of main clock transmission lines needs to be as brief as possible, directly and clear of thru-holes and power part to be able to avoid the crosstalk between clock and power. When multiple clocks with different frequencies are applied on a single PCB, two clock lines with different frequencies mustn't be taken care of parallel. However, for multiple components using clock indicators with the same frequency, network can be written by spider type, tree type and branch type.
In high-speed cryptographical cards, FPGA obtains 66.66MHz clock through the crystal oscillator on PCB. After looping with intrinsic hair inside FPGA, 200MHz basic clock is produced as the user interface for chip 2 and chip 3 to use clock. Then 100MHz clock is provided after intrinsic frequency dividing circuit as NiosII softcore and the working clock of hardware circuit inside FPGA. The divided frequency 16MHz is the working clock for chip 2 and chip 3 as the divided frequency 20MHz is the working clock for chip 1 and chip 4. Clock distribution is shown in Number 4 below.
High-speed signal tranny between PCIE slot machine and Personal computer is applied by high-speed cryptographical credit card in the form of differential set routing to avoid problems regarding signal integrity. In most cases, grounding cables aren't positioned between differential set indicators, otherwise coupling impact between differential set indicators will be damaged. Following the routing of differential set indicators, copper is positioned around PCB high-speed indicators with extra space fully filled up with grounding cables to increase circuit's EMI ability. The main element of PCB routing is to keep up the symmetry of differential pairs. If the space of differential pairs isn't compatible, the precision of data reading and writing will be affected with the info transmission rate reduced. To guarantee the system's validity of data reading within the same period, the delay difference between differential indicators needs to be preserved in an allowed category and the routing duration must be purely the same. Therefore, snake-shaped routing can be employed to solve this issue by modifying time delay. With this design, communication is applied by Computer through PCIE and cryptographical cards and the transmitting and getting of high-speed indicators are applied by differential set indicators with the distance of PCB routing managed within 25mil. The coordinating diagram of snake-shaped routing size is illustrated in Shape 5.