Why Is Ground Bounce Bad?

2019-12-11 15:31Writer: qyadminReading:

ground bounce in pcb

     Ground bounce is a form of noise that occurs during transistor switching. when the PCB ground and the die package ground are at different voltages. 

      To help explain the idea of ground bounce. take the example of the push-pull circuit below that can provide either logic-low. or logic-high output.

     The circuit consists of two MOSFETs. The upper p-channel MOSFET has its source connected to Vss. and the drain connected to the output pin. The lower n-channel MOSFET has its drain. connected to the output pin and its source connected to ground.

     These two MOSFET types have opposite responses to MOSFET gate voltages. An input logic-low signal at the MOSFET gates will cause the p-channel MOSFET to connect Vss to Output. and the n-channel MOSFET to disconnect Output from Gnd. An input logic-high signal at the MOSFET gates. will cause the p-channel MOSFET to disconnect. its Vss from Output and the n-channel MOSFET to connect Output to Gnd.

     Connecting the pads on the IC die to the pins of the IC package are tiny bonding wires. These mechanical necessities have a small amount of inductance. modeled by the simplified circuit above. There is some amount of resistance and capacitance in the circuit, as well. that are not modeled nor needed to understand the following overview.

     Three inductors shown in the equal circuit for a full-bridge switch. The inductor symbols. represent the package inductance (inductance inherent in an IC's package design). and the circuit output connected to some components (it is not allowed to float).

     Imagine encountering this circuit after the input held at logic low after a long period of time. This state would have caused the upper transistor to connect the output of the circuit to Vss. through the upper MOSFET. After a long period of time, stable magnetic fields would exist in LO and LA. and the potential difference for ΔVO, ΔVA, and ΔVB is 0 Volts. A small amount of charge will  stored in the trace.

     As soon as the input logic switches to low. the upper MOSFET would disconnect Vss from the output. and the lower gate would trigger the lower MOSFET to connect the output of the circuit to GND.

The bad of Ground Bounce

     The potential difference between output. and ground causes current to move down from the output to ground through the lower MOSFET. The inductors use the energy stored. in their magnetic fields to establish a potential difference up and across ΔVO. and ΔVB that try to resist changes in the magnetic field.
     Even though they connected. the potential difference. between the output and ground is not immediately at 0 V. Remember. that the output was before at Vss and the source of MOSFET B was before at 0 V potential. This previous potential difference will cause current to flow. while the output line discharges.
     At the same time that current is starting to. move from the output down to ground, the inductive properties of the package. create a potential difference across ΔVB and ΔVO to try to. maintain the before established magnetic field.
     The inductors LB and LO change the MOSFET source and drain potentials. That is a problem because the MOSFET gate voltage referenced to the ground on the die-package. The input voltage might no longer be enough to keep the gate open or cause it to open many times. as the circuit oscillates near the gate trigger threshold.
     When the circuit switches again. a similar set of circumstances will cause a potential to established across ΔVA. that decrease the source voltage of MOSFET A below a triggering threshold.
       Right now that the input changes state. the output and MOSFETS are no lengthier in a defined state—they are somewhere between. The result might be false switching or double-switching. Additionally, every other parts on the IC die that reveal the same Gnd. and Vss connections will harmed by the switching event.
      Besides the effects of surface bounce aren't limited to the IC die. as ΔVB forces the MOSFET source potential above 0V. it forces the circuit Gnd potential below 0 V. Most of. the images you see depicting bounce prove outside effects.
      If you have several gates switching at the same time. the effect compounded and can completely disrupt your routine.
      You can see jump in the examples below.
   Significant Gnd and Vss bounce shown in Figure 2 in a signal line from the BeagleBone Black computer. with the LightCrafter cape attached and activated.
   Here, roughly ~1V of noise developed on a 3. 3V line during transitioning that continues to resonate in the sign lines. before slipping to the background line noise.
Why Is Ground Bounce Bad?
  Figure 2. A transmission line from the BeagleBone Black. with the LightCrafter cap attached and activated.
  The noise is not limited to the entrances that are switching. the switching gates link to the ICs power pins. and PCBs often reveal common power and surface rails. That means that the noise communicated to other places. in the circuit either through direct electrical connection. via Vss and Floor on the die or coupling of the footprints on the PCB.
Why Is Ground Bounce Bad?
   Figure 3. This image captured from the BeagleBone Black with the LightCrafter cape attached.
  In Determine 3, Channel 2 (shown in cyan above) shows ground. and Vss bounce in an undamped transmission line. The problem is significant enough that it telegraphs. through to an alternative signal line on Route 1 (shown in yellow).

ground bounce reduce tips

     Use bypass capacitors to provide a stable voltage potential for the device and to contain the bounce effect to keep it from spreading out to the rest of the circuit.
     Place bypass capacitors as close as possible to each supply pin of the device. The closer you can place them the better as this will help to reduce the impact of the current spikes during switching, especially when several outputs are switching at the same time.
     Connect bypass capacitor pads to power and ground with wide and short traces and vias to minimize inductance and increase current flow.
     Connect each ground pin to the ground plane individually. Connecting the ground pins together in a daisy chain will increase the length of return ground path and create more inductance.
     Use current-limiting resistors to regulate the current flow in and out of your devices.
     Spread out the timing of the outputs in a device that switch so they don’t all switch simultaneously. Also, distribute these outputs evenly throughout the device.
     Eliminate the use of IC sockets as much as possible.
     Use separate power and ground planes to leverage the capacitance of the planes.
     Use SMD capacitors to minimize lead inductance.
     It is recommended to place a ground plane next to each power (VCC) plane. This placement gives zero lead inductance and no ESR. The dielectric thickness between the two planes should be ~5 mils.
     Another way that you can help yourself to reduce the possibility of ground bounce in your PCB design is to use tools that have been created for this task. You need a PCB design system with signal integrity tools for analysis and high-speed design features for precisely controlling your component placement and routing widths. With Allegro PCB Designer, you have all of this functionality ready to go to work for you.

Types of ground bounce in pcb


Ground Plane

     One common technique is to use a ground plane, which is a large piece of copper on a PCB. PCB manufacturers will cover all the areas that don’t have a component or trace on them. with the copper ground plane.
     In a two-layer board, the standard PCB ground plane rules state. that the ground plane should placed on the board’s bottom layer. while the components and signal traces are on the top layer.
     It is best to avoid creating a ring of conductive material formed by the ground plane. as this makes the ground plane more susceptible to electromagnetic interference (EMI). This conductive ring acts as an inductor, and an external magnetic field. may cause an electric current called a ground loop.

     You may end up with a conductive ring if placing the ground plane over the whole bottom layer. and then removing the parts that have electronic components. To avoid this issue, make traces as short as possible, and after mapping them. put your ground plane so that it runs underneath them. You may need to adjust the layout of traces. and components to avoid having to create conductive rings.
     The ground plane is also often on both sides of the board. In some cases, the plane on the component side  kept at the supply voltage. and the plane on the other side of the board grounded. The ground plane connected to the ground pins of the components. and connectors to keep the ground voltage at the same level through the whole PCB.
     On a two-layer PCB, you may also use more than one ground plane. Each plane should connect to the power supply. to keep the planes separated and prevent ground loops from occurring.

Ground Plane Vias

     If there ground planes on both sides of the PCB. they will connected through vias at many different places on the board. These vias are holes that go through the board and connect the two sides to each other. They allow you to access the ground plane from anywhere you can fit in a via.
     Using vias can help you to avoid ground loops. They connect the components to the ground points. which connect through low impedance to all the circuit’s other ground points. They also help to keep the length of return loops short.
       Pieces of copper, such as ground planes. may resonate at one-quarter of the wavelength of the frequency of the current. which is flowing into it. Putting stitching vias around the ground plane at specific intervals. can help to control this. A practical rule of thumb is to place ground vias at one-eighth of a wavelength or less. This works because a stub on a trace only starts to become an issue at one-eighth of a wavelength.
      To create vias, you drill small holes through the board. and pass thin copper wires. through them before soldering them on each side to form the necessary connections.

 Connector Grounds

     All the connectors in a PCB should connected to the ground. In connectors, all signal conducts must run in parallel. Because of this, you must separate connectors using ground pins.
     Each board will likely need more than one connector pin leading to the ground. Having one pin may cause issues with impedance mismatch, which can cause oscillations. If the impedance of two connected conductors does not match. the current flowing between them may bounce back and forth. These oscillations can alter the performance of the system and cause it not to work as intended. The contact resistance of each pin of a connector is low but may rise over time. For this reason, it is ideal to use many ground pins. Approximately 30 to 40 percent of the pins in a PCB connector should ground pins.
     Connectors come in various pitches and can have different numbers of rows of pins. The pins of a connector may also be parallel to the PCB surface or at a right angle to it.


     PCBs contain one or more integrated circuit chips, which need power to operate. These chips have supply pins to connect them to an external power source. They also have ground pins, which connect them to the ground plane of the PCB. Between the supply and ground pins. there is a decoupling capacitor, which serves to smooth out oscillations. in the voltage supplied to the chip. The opposite end of the decoupling capacitor connects to the ground plane.
     One of the main reasons for the use of decoupling capacitors. related to functionality. A decoupling capacitor can act as a charge storage device. When the integrated circuit (IC) requires more current. the decoupling capacitor can provide it through a low inductance path. Because of this, it is best to place decoupling capacitors close to the IC power pins.
     Another primary purpose is to reduce the noise put into the power and ground plane pairs and reduce EMI. Two main issues can cause this noise. One is a decoupling capacitor that does not provide adequate current resulting. in the lowering of the voltage at the IC power pin . The other is an intentional current sent between the power. and ground planes using a via with a fast-switching signal.
     You should choose the placement and number of decoupling capacitors for a design. based on their two functionalities. Often, distributing the capacitors across the entire board is the best approach. try placing some near the IC ground. and power pins to use. Using the highest value of capacitance is also recommended. and it is best to keep all the capacitors at the same value. You may also want to use a combination of high equal series resistance (ESR) and normal capacitors.


Ground bounce  history

     As system designers begin to use high performance logic families. to increase system performance. they may run into new problems which before did not raise concern. when lower performance devices utilized. These problems can generally avoided by following a few simple rules. This application note discusses. the subject of ground bounce about high performance CMOS logic families. and offers a set of simple guidelines that will drop system problems due to this phenomenon.
     Ground bounce has been a concern to some system designers for many years. Its effects can found in most bipolar and CMOS logic families. But, ground bounce has recently become a major issue. Although new advanced CMOS logic families have edge rates. comparable to advanced bipolar logic devices. CMOS outputs swing almost from rail to rail while bipolar outputs. swing from ground to approximately 3.0V. These edge rates, coupled with the greater voltage swings. found in today’s advanced CMOS logic devices. tend to generate more ground bounce noise than their bipolar counterparts.
     In 1982,Fairchild Semiconductor. began to develop FACT (Fairchild Advanced CMOS Technology) logic incorporating. more than three years of experience gained. with FAST (Fairchild Advanced Schottky TTL) logic into the groundwork. As a result. Fairchild was able to understand the important trade-offs. associated with high performance in a logic family. In the bipolar world, these trade-offs were between speed and power. in the CMOS world, the tradeoffs are between speed and ease of use. Utilizing experience gained from FAST products. the FACT family objectives defined to provide the greatest solution. allowing greater system performance while minimizing system design problems. Using FACT devices does need more attention toward circuit design. and board layout than older. slower technologies. The resulting advantages—low power and high performance outweigh these considerations.

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